Fixed Priority Arbitration of Platform Designer
Hi all,
I have a question regarding the built-in arbitration logic of the Platform Designer (not via an Arbiter IP, but via creating a "Slave arbitration scheme" in Interconnect Requirements. I'm using MAX10 FPGA with Quartus Prime 21.1 Standard Edition.
I want a system that a custom module X and the Nios2 core are the two masters of a slave B on the Avalon bus. I want to have the Nios2 to make the initial configurations etc on slave B but then I want slave B to obey the master X for almost the rest of the time. The Master X is also a slave of Nios2, but I'd like to use the Avalon bus for the data transfer between Master X and slave B. How should I set the arbitration in the Platform Designer then ? I can already choose "Fixed Priority" but then how does it switch between two masters in this case ? How can one master (in this case especially for the one with high priority) let go of one slave so that the other master with less priority can use it ? Given that the master X will be a custom written entity instead of an Intel IP, and the slave B has only Avalon interface in order to communicate with the rest of the entities in the FPGA; what things do I need to take into consideration ?
Any help is appreciated.
Cheers,