Fixed Point Multiplication in Verilog or Quartus II

Hello,

I plan to implement a controller digitally in my FPGA & it involves numerous fixed-point additions, multiplications & divisions.

Therefore here is a generic question:

Suppose I have to multiply two 16-bit signed fixed-point numbers with non-matching binary points, say

A = 1(sign bit) + I1 (integer bits) + F1 (fraction bits) = 16-bits

B = 1(sign bit) + I2 (integer bits) + F2 (fraction bits) = 16-bits

Depending on what range of data A & B will take, I have decided upon the position of binary-point in the result, let us say:

result_AxB = 1(sign bit) + I3 (integer bits) + F3 (fraction bits) = 16-bits

(I1, I2, I3 , F1, F2, F3 are all known)

So, how do I implement this ? ( as a Verilog code or in Quartus as a block diagram ... anything would help)