Fixed Point and DSP Usage

Technically DSP usage could be reduced by user lower precision; however, the compiler might not necessarily be able to correctly pack your lower-precision computation into DSPs. "Intel FPGA SDK for OpenCL Pro Edition Best Practices Guide, Section 3.3.1. Floating-Point versus Fixed-Point Representations" explain how you can infer fixed-point computation.

P.S. If you are using Arria 10 which has support for one FP32 Fused Multiply and Add per DSP, even in the best case you will be able to do one instance of (a * b) + (c * d) per DSP if all numbers are smaller than 18 bits, giving you one extra operation per DSP compared to FP32.