Fix current auto pin fit to prevent future chang

You open this dialog box by clicking Back-Annotate Assignments on the Assignments menu.

Allows you to copy device and resource assignments made during compilation into the Quartus II Settings File (.qsf), thereby preserving the current fit for future compilations. You can use the Back-Annotate Assignments dialog box (Default type) to preserve pin, cell, routing, or device assignments, or you can use the Back-Annotate Assignments dialog box (Advanced type) to preserve LogicLock regions and employ more advanced back-annotation options. You can select the back-annotation type in the Back-annotation type list.

I also don't agree with letting Quartus fit the pins instead of you. I usually do a combination, but in reality Quartus doesn't know what your board layout is. So if you have a flash device above the FPGA, make sure the flash interface pins are put there. If Quartus puts them up there but they're in the reverse direction of the way the flash is laid out(resulting in a tornado board route), then flip them. I feel designers have more information and are smarter about this then Quartus.

Is what Quartus can do is fit for timing. So if you're flash comes in and needs to feed an output pin in one cycle, it won't place them on opposite sides of the FPGA. The nice thing is that if you put them on opposite sides, and have entered timing constraints, you'll get paths with negative slack(in red) alerting you to the issue.

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You open this dialog box by clicking Back-Annotate Assignments on the Assignments menu.

Allows you to copy device and resource assignments made during compilation into the Quartus II Settings File (.qsf), thereby preserving the current fit for future compilations. You can use the Back-Annotate Assignments dialog box (Default type) to preserve pin, cell, routing, or device assignments, or you can use the Back-Annotate Assignments dialog box (Advanced type) to preserve LogicLock regions and employ more advanced back-annotation options. You can select the back-annotation type in the Back-annotation type list.

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Yes, this is right the function I am looking for. Thank you very much!

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I also don't agree with letting Quartus fit the pins instead of you. I usually do a combination, but in reality Quartus doesn't know what your board layout is. So if you have a flash device above the FPGA, make sure the flash interface pins are put there. If Quartus puts them up there but they're in the reverse direction of the way the flash is laid out(resulting in a tornado board route), then flip them. I feel designers have more information and are smarter about this then Quartus.

Is what Quartus can do is fit for timing. So if you're flash comes in and needs to feed an output pin in one cycle, it won't place them on opposite sides of the FPGA. The nice thing is that if you put them on opposite sides, and have entered timing constraints, you'll get paths with negative slack(in red) alerting you to the issue.

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And the fitter mixed up I/O pins of all 7 ports in my design. Looks chaos XD.

Ah... That is strange... I can not drag them from the left Node Name list. Do I miss something? I have pressed down the Assign Down button.

My Quartus II version 7.1 Build 178 06/25/2007 SJ Web Edition

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I know how to drag it now. It is tricky. Give it a click to select it first, the color will toggle, then release mouse button and click on it again to drag it.

Rysc;

Looks like we killed this one, good working together.

Am interesting aside, while reading your comments you referred to a term I had not heard of before, "If Quartus puts them up there but they're in the reverse direction of the way the flash is laid out(resulting in a tornado board route), then flip them."

"Tornado". In my board routing days, we referred to these as "Haystacks".

Interesting difference in visuals.

Cheers,

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