Honored ContributorI am importing a latch based design into stratix IV.
(No, It is beyond my paygrade to change the RTL or netlist to remodel latches) I find that fitter time really goes up on latch based designs. The latch is modeled as a self-looping LUT. Any Fitter options that can make it go faster? Thanks for any advice.
Honored ContributorIf latches are inferred(i.e. Quartus recognizes them as latches) then it will time them like a register. But if it's physically designed as a loop, it may not recognize it's a latch. If that's the case, your design is just a huige combinatorial block with tons of loops. I'm guessing timing analysis croaks on that, which is where your fit time is spent. Just a guess. But if you can't change anything, perhaps "set_scc_mode -size 1" would help TQ run faster. Just a guess though.
Honored ContributorUnfortunately, the command is only available in
STA: ERROR: Quartus II Tcl command "set_scc_mode" is only available for use in the following executable: quartus_sta while executing "set_scc_mode -heuristic"
