Forum Discussion
Altera_Forum
Honored Contributor
14 years agoIf latches are inferred(i.e. Quartus recognizes them as latches) then it will time them like a register. But if it's physically designed as a loop, it may not recognize it's a latch. If that's the case, your design is just a huige combinatorial block with tons of loops. I'm guessing timing analysis croaks on that, which is where your fit time is spent. Just a guess. But if you can't change anything, perhaps "set_scc_mode -size 1" would help TQ run faster. Just a guess though.