Honored Contributor
Honored Contributorend
end
always @(negedge clkadc_045) begin
for (integer i = 0; i < adcnbits + 1; i = i + 1 ) begin : reg_lvds1
adc_lvds_out[desfactor*i + 1] <= adc_data_src; end end always @(negedge clkadc_315) begin for (integer i = 0; i < ADCNBITS + 1; i = i + 1 ) begin : REG_LVDS2 adc_lvds_out[DESFACTOR*i + 2] <= adc_data_src;
end
end
always @(posedge clkadc_045) begin
for (integer i = 0; i < adcnbits + 1; i = i + 1 ) begin : reg_lvds3
adc_lvds_out[desfactor*i + 3] <= adc_data_src; end end 3) Then I register all the data one more time using clkadc_315 (I have an overrun bit as well as the ADC data and my data is inverted so ignore that stuff): always @(posedge clkadc_315 or negedge adc_reset_n) begin if (~adc_reset_n) begin adc_or <= {DESFACTOR{1'b1}}; adc_data <= {(DESFACTOR*ADCNBITS){1'b1}}; end else begin adc_or[DESFACTOR-1:0] <= ~adc_lvds_out[DESFACTOR*(ADCNBITS+1)-1:DESFACTOR*ADCNBITS]; adc_data[DESFACTOR*ADCNBITS-1:0] <= ~adc_lvds_out[DESFACTOR*ADCNBITS-1:0]; end end 4) Then I added my timing constraints in the SDC file (input clock is half the clock frequency for me) set lvds_data_tracemax 0.05 set lvds_data_tracemin 0 set lvds_clk_tracemax 0.05 set lvds_clk_tracemin 0 set lvds_tco_min -0.260 set lvds_tco_max 0.120 set lvds_maxdelay [expr $lvds_data_tracemax - $lvds_clk_tracemin + $lvds_tco_max] set lvds_mindelay [expr $lvds_data_tracemin - $lvds_clk_tracemax + $lvds_tco_min] create_clock -name clk_adc -period ${Tadcin}ns # Rising edge constraints set_input_delay -clock [get_clocks clk_adc] -max ${lvds_maxdelay}ns [get_ports HSMC_RX_p*] set_input_delay -clock [get_clocks clk_adc] -min ${lvds_mindelay}ns [get_ports HSMC_RX_p*] # Falling edge constraints set_input_delay -clock [get_clocks clk_adc] -max ${lvds_maxdelay}ns [get_ports HSMC_RX_p*] -add_delay -clock_fall set_input_delay -clock [get_clocks clk_adc] -min ${lvds_mindelay}ns [get_ports HSMC_RX_p*] -add_delay -clock_fall # Mutlicycle Paths # http://quartushelp.altera.com/14.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_set_multicycle_path.htm set_multicycle_path -setup -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_045] 2 set_multicycle_path -hold -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_045] 1 set_multicycle_path -setup -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_315] 2 set_multicycle_path -hold -start -from [get_clocks clk_adc] -to [get_clocks $clkadc_315] 1 6) I may have done my timing delays wrong because what ended up happening is the fitter inserted a delay from posedge clkadc_045 to the register so in the end the order was 3 0 1 2 instead of 0 1 2 3. In your case, the ADC CLKOUT is center aligned with the data so you have other options. If you want to deserialize by 4, like I did, your phase shifts would be 0 and 90 degrees. Then register the data on the pos and neg edges of both of those. Alternatively, to deserialize by 2 you can just use the pos and neg edges of your incoming clock (or PLL with same frequency and 0 phase shift).
