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Altera_Forum's avatar
Altera_Forum
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14 years ago

FIR filter implementation in Cyclone II

Hi,

I am trying to implement a FIR filter written in verilog in Cyclone II.

The filter coefficients are generated using winfilter.exe software (Fs = 50kHz, Fcutoff = 3kHz).

This piece of software generates code in VHDL.

I have converted it to verilog. As far as I can say, the conversion is OK.

The output of the filter to a simple sine wave of 1kHz looks like a mess (just some pulses of different widths and heights). I am attaching my verilog code. Can somebody point me to what could be the problem or how can I debug the issue?

I am new to implementing DSP filters in FPGA's so not able to understand how to debug the issue.

Thanks,

Aditi.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You should create a testbench for the filter.

    The first test to implement is the impulse response of the filter.

    You do this by generating an input data sequence consisting of the largest positive word, eg. 7Fh for an 8-bit 2's compliment number, followed by zeros.

    The impulse response at the output should match your filter tap coefficients multiplied by 7F, and then truncated/rounded by whatever your multiplication logic implements.

    If your filter output preserves all product bits, then you could just use a logic 1 for the impulse, and the output will be your filter taps, or, you might prefer to use an input of 0100_0000b = 40h, since then you just right-shift the filter taps, and truncate/round.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    There is a lot that can be said about your code. But most important your clocking scheme is not right (for fpga). you are using several gated clocks. That could mess up your logic and later will lead to hold time violations in synthesis..

    Your clock is 48MHz and your data arrives at 50KHz i.e. one sample every 960 clocks. So for delay pipe activate a shift on 48MHz using clk enable pulse every 960 clocks.

    for multiplication, run on 48MHz. At every 960 pulse run a counter from 0 to 31 but stop at 32. At every count from 0 to 31 multiply an input stage with a coeff meanwhile accumulate from count 0 till count 31.

    at count 32 when all is done update your output from accumulator result and set accum and counter to zero. Repeat this cycle at next 960 pulse.

    One other note. You have 32 coeffs all held in registers plus reset. This is not needed as it wastes 32*16 registers. Since they are constants you should use wires and thus avoid also timing demands.

    finally once your filter is alive and since your cutoff is pretty sharp (.06 of Fs)and your speed is high enough you may use a much larger filter (possibly 100 taps or so but depends on your requirements really) at small cost on accumulator width.