FIR filter implementation in Cyclone II

There is a lot that can be said about your code. But most important your clocking scheme is not right (for fpga). you are using several gated clocks. That could mess up your logic and later will lead to hold time violations in synthesis..

Your clock is 48MHz and your data arrives at 50KHz i.e. one sample every 960 clocks. So for delay pipe activate a shift on 48MHz using clk enable pulse every 960 clocks.

for multiplication, run on 48MHz. At every 960 pulse run a counter from 0 to 31 but stop at 32. At every count from 0 to 31 multiply an input stage with a coeff meanwhile accumulate from count 0 till count 31.

at count 32 when all is done update your output from accumulator result and set accum and counter to zero. Repeat this cycle at next 960 pulse.

One other note. You have 32 coeffs all held in registers plus reset. This is not needed as it wastes 32*16 registers. Since they are constants you should use wires and thus avoid also timing demands.

finally once your filter is alive and since your cutoff is pretty sharp (.06 of Fs)and your speed is high enough you may use a much larger filter (possibly 100 taps or so but depends on your requirements really) at small cost on accumulator width.