Forum Discussion
Oliver_I_Sedlacek
Contributor
ContributorFIR filter implementation doesn't use Cyclone DSP blocks
I've coded up an FIR filter in VHDL that uses up to 10 clocks to multiply sample pairs by filter coefficients and accumulate the results. This seems to work but Quartus implements this all as logic, ...
Hi,
Please refer this coding style to infer DSP block.
dsp-block-vhdl-inferring-a5c5-figure-7.jpg (748×397) (intel.com)
dsp-block-vhdl-inferring-a5c5-figure-8.jpg (809×390) (intel.com)
Thank you,
Kshitij Goel
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
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Thank you,
Kshitij Goel
