FIR filter coefficient calulation: $sin usage during synthesis/elaboration

Hi Marcus,

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Now, I know that $sin can't be synthesized, but I'm using it in a context where it should be evaluated during elaboration and turned into a constant. There is no need to synthesize the $sin function. Does anyone know of a way to do this cleanly, or is Quartus too rigid for this?

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In VHDL, I use functions like this to initialize constant's, and then those constants get used in the body of the code, i.e., inside process statements.

Perhaps your Verilog needs some intermediate constants too. Its hard to tell without seeing the complete code.

Cheers,

Dave