Filter iir trasposed structure

Ok so you get wrong zero after every output.

Your coding is too much for such a simple task and I don't see any feedback to adder. In fact adder(1) seems undriven.

May be the best way is to see following code to implement what you do (basically an accumulator):

process
begin
wait until clk = '1';
   y_d <= adder_output & '0';   -- delay stage and multiply by 2 using shift
end process;
...outside clocked process, y_d is fedback as input to adder
adder_output = xin + y_d;

you will need to look after type and size issues