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I don't quite get it. I assume your simple test filter is y(i) = x(i) + 2*y(i-1)
thus you need one delay stage for output (y) to be added to input (x) [obviously you don't need any multipliers for this example).
You should not put any delay on multiplier outputs but just one on adder output to serve as one delay stage as well as assist timing.
x => *1 => + => register => *2 => back to +
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Thank you for your response.
Ok, the equation of the filter is ok..
I choice to implement an transponse structure, so in the process the instruction (first program iir_1 without delay..)
adder(0)<=pnum(0)+pden(0)+adder(1)
where these are signal so this register is update at the end of the process..
I use the lpm.mult because the signal is std_logic_vector so i implement with these megafunction the moltiplication 1*x and 2*y.
the problem is that.. the signal pden (auto-regressive part) is summed with one cycle of delay.. image 01 (y_out)
the correct development of the output is showed in the image iir_1_ok.pdf So.. i try to introduce a delay of the first part (moving average part 1*x) to sum this with the second part correctly.. but i don't do this well..:confused: because the signal become zero after the sum of the first two number. (10-20-0-0-0-0-ecc..). I expect to see (10-20-40-80-160 ecc...)
This is only the first tap of a generic iir filter order.. if this structur function correctly i can add other part using array..
do you understand?
thank you! :o
by Kikko
Honored Contributor
