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Altera_Forum
Honored Contributor
10 years agoThank you Tricky. Yes you are correct, the bus declaration for the address is 0 to 4095, I deleted accidently the line when I try to isolate the problem and coppied the code into a different file. (No wonder, my brain was thinking any more after 13 hours at work).
The code was running over the time in Xilinx, Lattice, Orca (ATT FPGA) and also in 10k100 (altera), and was compiled with the tools at the time available for those FPGAs. It is the first time that Quartus is used at our company, and this code is compiled with this compiler. The last projects with Altera FPGA dated back to 1998. (In the far end of our building are still some old computer with CRT monitors running Max II under windows 95.) However, I came to the same conclusion that Quartus compiler does not support VHDL file read ROM configuration. (Could also just be a bug sine the complier does read the file size correctly (opens the file and finds the EOF, but does not fetch the data. I found other deviations form IEEE 95 standard in Quartus compiling that that are definitive software bugs.) Our application is very mission critical. And for each different target system we need to create different analog behavior files. The analog data gets created from the simulator and are provided in that “4k” file. I think for right now I have only option 1 available; manually declare an array in VHDL. (Since this impacts the least hand manipulation on the provided analog data file. It is a pain in the b… since I need to change the VHDL file each time.) I tried 2 but we would have to make manually too many changes in the file, that’s too risky. I was looking into the possibility load the data into the flash after compiling the code, by read the data file into flash via USB cable. That would be the most elegant method we would not have to create for each target a different FPGA image anymore. However, the only Flash IP I find supporting the MAX10 Family uses the Avalon interface. I was looking for the user-flash with a parallel interface, but the IP does not support Max10 family. The issue I have is that the Avalon interface requires an on chip microprocessor and firmware. My problem firmware and software is a NO_GO for this type of application. Any thoughts on that?