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Altera_Forum
Honored Contributor
Honored ContributorFile not simulating with ModelSim-Altera
Hello guys, I have the following two projects. The first one Simulates perfectly in modelsim-altera, but the second one does not show output. I want to know where is the problem in the second one??? ...
Altera_ForumHonored Contributor
Honored ContributorDo not mix in your design registers clocked from falling and rising edges except you are implementing DDR registers. If you are using single edge use only risig edge.
--- Quote Start --- Now, do you think I could extend your code to divide by (4,6,8,......)??? Thank you for your help really. --- Quote End --- Yes you can. Add counter which is incremented every clock cycle. Toggle clk_div signal when counter reaches certain amount (depends on divide by value), reset counter.
