File not simulating with ModelSim-Altera

Do not mix in your design registers clocked from falling and rising edges except you are implementing DDR registers. If you are using single edge use only risig edge.

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Now, do you think I could extend your code to divide by (4,6,8,......)??? Thank you for your help really.

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Yes you can. Add counter which is incremented every clock cycle. Toggle clk_div signal when counter reaches certain amount (depends on divide by value), reset counter.