File not simulating with ModelSim-Altera

Hi,

I think there is something with output port type declared as a buffer. I never use ports declared as a BUFFER. Use signals and assign them to output ports. I would change your code to something like this:

---------------------- Frequency division by 2 -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------
ENTITY freq_div2 IS
    PORT ( 
            clk     : IN STD_LOGIC;
            reset_n : IN STD_LOGIC;
            out2    : OUT STD_LOGIC);
END freq_div2;
-----------------------------------------
ARCHITECTURE example OF freq_div2 IS
signal clk_div : std_logic;
BEGIN
PROCESS (clk, reset_n)
    BEGIN
        IF reset_n='0' THEN
            clk_div<='0';
        IF (clk'EVENT AND clk='0') THEN
            clk_div<= NOT clk_div;
        END IF;
    END PROCESS;
    
out2<=clk_div;
    
END example;

By the way why is yor process trigered from falling clock edge?