Forum Discussion
Occasional ContributorFIFO:How to slow down the clock Frequency from 50 Mhz
once I enable your counter, it is writing at full clock speed to the fifo
once the fifo is full, the counter just continues counting
by the time it start reading and printing the first value to the serial port, the fifo is probably already overflowing, as I did print some hello word message. Printing to the serial port is very slow compared to the counter filling up your fifo, and counter counts at something like 50MHz I guess (?)
* once the fifo starts overflowing, not all counter values will go into the fifo, as it is full, and you're only slowly reading the values from the fifo
17 Replies
JOHIContributor
Hello,
50 Mhz is the clock speed used by the CPU to process assembler instructions.
Instructions can require multiple clock pulses, this depends also on the cpu type.
You are looking at a way to slow down the loop:
#include <stdio.h> #include <unistd.h> int main() { while (1) { printf("Hello from Nios II! \n"); usleep(1000000); } return 0; }Best Regards,
Johi.
SS5I have added "usleep(1000000)" but printing speed is slow but i am getting correct answer.
Can u check my FIFO design.
- GuaBin_N_Intel
I think the best way to control the flow of counter instead of slowing down the whole system. Probably you use the almost full signal from the FIFO to stop or disable the write signal from the counter. Currently ,the module "block count" always receive data from counter regardless of any condition. Hope this helping you.
- SS5
Thanks for your response.
I am new to the altera.
>>Probably you use the almost full signal from the FIFO to stop or disable the write signal from the counter.
How it can done , can you explain me briefly.
Thank you
- GuaBin_N_Intel
It's harder in explanation if you design it in schematic. I make it simpler here:
1) Invert almost full signal from FIFO
2) "ANDed" it with the enable of counter
3) Drive output of "ANDed" signal to both of write FIFO and enable of counter. This is to halt the transfer completely.
- SS5
Did you mean to create own FIFO IP ?
1) Invert almost full signal from FIFO
2) "ANDed" it with the enable of counter
3) Drive output of "ANDed" signal to both of write FIFO and enable of counter. This is to halt the transfer completely.
Sorry to ask silly questions. In NIOS, i need to do ??
- GuaBin_N_Intel
The method does not involve any NIOS software or C coding. It is done through logic level. You have to modify the circuitry in the schematic and use primitive logic to construct.
- GuaBin_N_Intel
- SS5
Really sorry, i am not able to understand your logic level flow. can you explain in a better way like schematic diagram.
I need your help to complete this process. But Finally, i need to communicate with NIOS. Because through WIZNET i need to communicate with PC.
Thanks
- SS5
But Finally, i need to communicate with NIOS. Is it possible with designs building with primitive logic diagrams ? ?
