Forum Discussion
SS5
Occasional Contributor
Occasional ContributorFIFO:How to slow down the clock Frequency from 50 Mhz
once I enable your counter, it is writing at full clock speed to the fifo once the fifo is full, the counter just continues counting by the time it start reading and printing the first value to the...
GuaBin_N_Intel
Contributor
ContributorIt's harder in explanation if you design it in schematic. I make it simpler here:
1) Invert almost full signal from FIFO
2) "ANDed" it with the enable of counter
3) Drive output of "ANDed" signal to both of write FIFO and enable of counter. This is to halt the transfer completely.
