FIFO Controller. Help!

Hi! I'm having a problem implementing this:

A 16 level deep Circular FIFO is to be used between two asynchronous systems (Transmitting / Receiving). Implement the FIFO Controller Assuming that the FIFO is made of a 16x8 RAM array.

http://i249.photobucket.com/albums/gg240/badalandabad23/FIFOCONTROLLER.jpg

When wen is high, data can be written to the FIFO. When ren is high, data can be read from the FIFO. Writing has proirity over reading in case they occur simultaneously.

Address pointer ptr[3:0] serve as memory address line for the RAM array, while wr and rd are active high signal used to enable writing and reading respectively.

Flags:

ff = full flag, set when FIFO is full. No further writing is allowed when ff is set. Clear at reset.

hf = half flag, set when FIFO has exceeed its half depth. Clear at reset.

ef = emplty flag, set when FIFO is empty. Clear at reset.