I am using FFT megaCore as the core of my digital spectrum analyzer FFT core paramters: N=64, streaming mode, 8 bit inputs and output. However, in the vector waveform file that I made the simulation on FFT megaCore, the source real and imaginary have noise and I just want to capture the output at negative edge of the clock because those values are stable values that I wanted. I think of using negative edge-triggered D-Flip flop to store value when at the negative-edge of clock by using the source_sop and source_eop to enable the the D-flipflop. but that 2 signal only peaks for a short time. May I know how can I use this 2 signals to enable the D-flipflop or is there any better way to capture stable values from FFT megaCore?

You can capture the output data of the FFT on the positive edge of the clock, there is no problem. What do you want to do with the output data of the FFT ?

Bc when I capture data at positive edge, it seems to be noise value.. then I observe the value, only values at negative edge are stable values... therefore i wan to capture values at negative edge by designing the negative edge D-flipflop to capture it.. But I need to use signals to enable the D-flipflop... so that it wil capture only the stable value.

You mean that if you put flip-flops to capture the output data of the FFT, the value after the flip-flops are not the same than the value outputed by the FFT ? Can you put a picture of your simulation, because there is no reason this happen.

I have uploaded the simulation output from the FFT. I have highlighted the noise that occurs (i not sure whether is noise or nt). Because these random values exist in the simulation output, so i would like to capture value at negative edge of clock

These transitions should not happen, it is not a normal behaviour. 1. Your input data change a little bit after the falling edge of the clock. Why ? They should change on the rising edge of the clock. 2. The source_sop and source_valid signal don't change on a rising edge of the clock, this is not normal. Have you an explanation for this ? The clock signal on the simulation is it well the clock provided to the FFT ? Moreover it is precised in the avalon interface specifications (§ 6.2.2) that : --- Quote Start --- All outputs from a source interface to a sink interface, including the data, channel, and error signals, must be registered on the rising edge of clock. --- Quote End --- So everything must be done on the rising edge of the clock.

FFT megaCore usage problem | Altera Community

19 Replies

Altera_Forum
Honored Contributor
15 years ago
The source_sop and source_valid are not rising at the same time, this problem I also didnt know why this happens like this, These 2 signals are controlled by the control unit (CU.vhd). Could you please take a look on my CU.vhd file?
Altera_Forum
Honored Contributor
15 years ago
Hi,

Sorry for the delay of answer, I was quite busy with the work.

I test your project, and I don't get the same problem as you. So I think the problem comes from the waveform file you defined.

I attach the result of simulation (I put manually random value for the inputs), and the waveform input file I used. Maybe try with this file to check that you have something working well. Then check with your waveform file what is wrong. You can also send your waveform file, I can look at it.
multiple-attachments.zip104 KB
Altera_Forum
Honored Contributor
15 years ago
Hi, thanks for you reply.

I have run again the vwf you provided but I cant get the same simulation as yours. This simulation result I attached as the fft_h_resimulate.vwf. The sink_valid and sink_sop cant rise at the same time as compared to your original simulation, it seems like there is delay in my simulation and there are noise just at the rising edge of clock for output value sink real and imaginary.

I also attached my previous simulation. The input value is a 1kHz sine wave that I get it from Matlab but I key in manually in the waveform editor. Hope you can find the problem for my simulation.
Thanks.
multiple-attachments.zip13 KB
Altera_Forum
Honored Contributor
15 years ago
I really don't understand how you get these results. I take the vhd files you provided, and use the wvf and I have no problem. I try also with your waveform file and I don't have problem.

The simulation mode you use is it "functionnal" (Menu "Processing" -> "Simulator Tool") ?

Else I would advise you to create your test bench file and use ModelSim instead of the Quartus Simulator.
Altera_Forum
Honored Contributor
15 years ago
I am using "Timing" mode in the Simulator Tool there... Is it because I did the simulation in timing mode that result in all these random value or noise?

I would like to ask in my control unit, I would like to control the source_ready signal where this signal is '1' when the data_real is available and '0' when the data_real is not available
Can I do the coding like this?

if(data_real) then
source_ready<='1';
else
source_ready<='0';
end if;

in my vhdl code of CU.
Altera_Forum
Honored Contributor
15 years ago
Hi,
So try to simulate with the functionnal mode to see if it works as you want.
Normally, what you check with the simulation is the functionnal behaviour, and the timing violation are checked by Quartus with the TimeQuest tool.

About your question for generating source_ready, you cannot do what you propose directly. If you want what you can do is to put data_real to "XXXXXXXX" when there is no data, and then make the following test

if (data_real = "XXXXXXXX") then source_ready <= '0'; else source_ready <= '1'; end if;

But this kind of things works for simulation, not synthesis.
Altera_Forum
Honored Contributor
15 years ago
Hi,

I would like to ask about the reading of output

I am using Nios2 to design my c file to read the output from the fft core of my design...
I am combining the fft output 8 bit source_real, 8 bit source_imag and 6 bit source_exp into 1 22-bit signal output_int..
I am using the command IORD to read my 22-bit signal into an array in c and i declared the array as alt_32 output[64];
Now I would like to use separate the combined into its original 3 parts.. So, may I know how I can separate the combined signal back to its 3 individual signal of 8bit, 8 bit and 6bit?
Altera_Forum
Honored Contributor
15 years ago
Hi,

I see two ways to do it. Either you can use three addresses to access the FFT results, so you have something like this in your C code :
real = IORD(FFT_BASE, REAL_REG); imag = IORD(FFT_BASE, IMAG_REG); exp = IORD(FFT_BASE, EXP_REG);
Or, you can use one address and separate the data in the C code like this :
data = IORD(FFT_BASE, DATA_REG); real = (data >> 14) & 0xFF; imag = (data >> 6) & 0xFF; exp = data & 0x3F;
Is this answer your question ?
Altera_Forum
Honored Contributor
15 years ago
Hi, I am very new to the usage of this FFT Megacore function.
I recently just wanted to try out this FFT Megacore function to see how it works.
I tested the testbench file provided by LETS. I encountered error messages upon running the file in Quartus II. May I know if there is a recent update of it? Pardon me, I am very new in this and am interested to learn (I only have basic vhdl knowledge). Any help will be much appreciated.

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