Hi,
So try to simulate with the functionnal mode to see if it works as you want.
Normally, what you check with the simulation is the functionnal behaviour, and the timing violation are checked by Quartus with the TimeQuest tool.
About your question for generating source_ready, you cannot do what you propose directly. If you want what you can do is to put data_real to "XXXXXXXX" when there is no data, and then make the following test
if (data_real = "XXXXXXXX") then
source_ready <= '0';
else
source_ready <= '1';
end if;
But this kind of things works for simulation, not synthesis.