Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

FATAL ERROR while loading design "# Error loading design"

Greetings everyone!

My problem here is regarding on the testbench where it shows fatal error while loading at the end of the modelsim simulation. Precisely, the errors are about as follows:

i)# ** Error: (vsim-3389) C:/Users/Rheeshaalaen/Desktop/sw_pe_affine/sw_gen_testbench.v(91): Port 'i_lgap' not found in the connected module (8th connection).

>>>> Region: /sw_gen_testbench/pe_block[0]/genblk1/pe0 (how do i actually to find this region and i could not find it at all)

ii)# ** Error: (vsim-3389) C:/Users/Rheeshaalaen/Desktop/sw_pe_affine/sw_gen_testbench.v(91): Port 'o_rgap' not found in the connected module (15th connection).

>>>>> Region: /sw_gen_testbench/pe_block[0]/genblk1/pe0 (same problem as stated above)

Would any of you able to help to solve this problem and i would like say thanks in advance. Your help genuinely appreciated.

regards,

Rishi

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I think you need to show us the section of code that resulted the errors in sw_gen_testbench.v. And declaration for the module instantiated there.