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2 Replies
- Altera_Forum
Honored Contributor
--- Quote Start --- i have this problem when i do incremental compilation and i dont know why. *** Fatal Error: Access Violation at 0X181ABD9A Module: quartus_fit.exe 0x12BD9A : VPR_QI_FACADE::operator= + 0x12AD4A (fitter_vpr20kmain) End-trace please help me bye thanks --- Quote End --- Which Quartus Version and which FPGA do you use ? What happens when you switch the incremental compilation off ? - Altera_Forum
Honored Contributor
hello,thanks for reply, my version is the 7.2 and i have discover that the problem is because i put a logiclock region in reserved when there is any signal tap signal in this block
thanks bye