Altera_Forum
Honored Contributor
16 years agoFast Output Enable
I've got 16 bidirectional pins and I want the registers as close as possible to the pad to cut down on any routing delays between the last register and the pad on the output side and the first register and the pad on the input side.
The input side is working great using the FAST_INPUT_REGISTER constraint. On the output side, I've got constraints for FAST_OUTPUT_REGISTER and FAST_OUTPUT_ENABLE_REGISTER. The problem is that the bus is 16 bits wide but there is only one output enable bit. I was hoping Quartus II would be able to figure out that it needs to duplicate this register 16 times and place the close to the pads but it isn't happening. Looking in TimeQuest at the placement coordinates, I can see that the data bit registers are right next to the pads but the output enable register is not because it is shared across 16 pads and the skew is very large across the 16 bits of my bus. Anyone have any thoughts on how to resolve this? I tried creating 16 separate output enable registers but the tool just optimized them back to one register, even when I specified constraints to keep the registers. Any thoughts?