False path question - internal counter bit vs FSM state bit

Dear Altera Forum members...

This is my first post here :)

I have a sub-circuit that consists of a binary up-counter (LPM_counter) with asynchronous reset and count enable, and a comparator (LPM_compare).

The sub-circuit compares an input 5-bit vector to the count value and sets an output flag if the count value is greater-or-equal to the input data value.

This flag is used as a control bit to a finite state machine.

When running the TimeQuest timing analyzer tool in Quartus, I get setup timing violations with worst-case timing paths that involve the q[1]-bit and states of the FSM. My question is whether or not I can set these as false paths

https://alteraforum.com/forum/attachment.php?attachmentid=14298&stc=1

The figure shows how the TimeQuest labels the nodes that violate the setup timing.

I was thinking that since the timing violations does not involve the flag used to control the state transitions, I can set the shown paths as false paths... Please comment.

Regards Ronny