False path question - internal counter bit vs FSM state bit

The project uses the MAX V 5M80ZM64I5 device.

There are three auto-generated VHDL files: lpmcompare.vhd, lpmcounter.vhd and lpmzerotimeflag.vhd.

The lpmcountandcompare.vhd, connects them together as a subcircuit.

The toplevel entity is the timingtest_lpmcc_minifsm.vhd.

The .sdc file is called timingTest_LPMcc_miniFSM (there is only one constraint, the "create_clock"...)

Recall that Quartus by default uses 3-space wide tabs, such that the text-files may not look that nice in other text-editors...