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Honored Contributor
Honored ContributorFalse path question - internal counter bit vs FSM state bit
Dear Altera Forum members... This is my first post here :) I have a sub-circuit that consists of a binary up-counter (LPM_counter) with asynchronous reset and count enable, and a comparator (LP...
Altera_ForumHonored Contributor
Honored ContributorHi kaz.
In your comment "likely you are clocking wrong", will you please elaborate what that means ? The clock is generated externally. It is defined using the "create_clock"-command in the sdc file... In another example, using a max V CPLD with vhld code of a circuit that involves an LPM_counter and an LPM_compare - connected to a very basic FSM, I still cannot close timing for a 100 MHz clock (Fmax = ~97 MHz)... Do you think my code is faulty ?
