New ContributorHi all,
I am working on PCI-e design example where I tried to generate pci ip . When I tried to simulate via questa sim, I am getting fatal error due to BAR disabled. Please help me in resolving it. attached the error message and IP features provided while generating IP.
Regular ContributorHi,
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with findings.
Thank you for your patience.
Best regards,
Wincent_C_Intel
Regular ContributorHi,
Apologize for late reply.
Can I know which design example you are using?
If you have time can you please try out some design example in Intel FPGA store and see if the error is replicable ?
Do you try to configure the BAR before you try out the problem
Please check the user guide Session 6.8.3 Examples of Reading and Writing BAR0 Using the CRA Interface, to ensure everything is well set.
https://www.intel.com/programmable/technical-pdfs/683724.pdf
Let me know if you still facing the same problem.
Regards,
Wincent_C_Intel
New ContributorHi ,
This design example i am trying to execute. compilation is done but after that to connect with questasim for simulation, its showing error for generating testbench.
Here I am using quartus prime pro edition (21.4 version) with questasim simulation tool.
Regular ContributorHi,
Regards,
Wincent_C_Intel
Regular ContributorHi
We do not receive any response from you to the previous suggestion that I have provided.
Based on our support policy this thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you for understanding
Regards,
Wincent_C_Intel
