Failed Paths

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So i undestand well every possible net in the design is analyzed by the timing analyzer and for every net are calculated the time parameters (hold for example). In the specified case of the hold violation If i hae a vilation of 5 ns it means that the delay from the "from" register to the "to" register there is a delay of 5 ns respect the edge of the clock of the "to" register. If some of these register do not have a direct connection but there is ome logic in the path this warning can be non so important. How I can identify which warnig is really important. My project is old and made without all the altera recomendation about clocking scheme and so on...

Tx and Best Regards.

Stefano

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Hi,

is it a Clock Hold time vioaltion ? Can you please list one of the paths ?

Kind regards

GPK