Failed Paths

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You mean that for all possibly path in the design the is the analysis? I saw some reports where "from" and "to" are not directly connectd but through some logic. Wht does it mean an and hold violation of 5 ns if "from" and "to" are not directly connected?

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Hi,

the classic timing analyzer generates several reports:

Clock Setup : (clock_name)

Clock Hold : (clock_name)

These are the timing results for all register-to-register paths in your design. When you have Clock Setup violation your design is too slow. Clock Hold violations are often caused by clock skew (e.g in case of gated clocks).

tsu + th:

This reports your input timing. The paths from the input pins to register.

tco:

This reports your output timing. The paths from registers to output pins.

tpd:

This is the so-called propagation delays, which describes the timing of paths without registers through your device.

Kind regards

GPK