Altera_Forum
Honored Contributor
11 years agoExport partition netlist with blackbox
Hello,
I need to export post-synthesis netlist of entity A (all written in VHDL) as *.qxp Deep in hierarchy of entity A there is instance entity B (written in Verilog). The entity B should be defined when netlist of component A is used, so that component B could be defined later. Now I have VHDL component of entity B defined in file where entity B is instantiated, but Quartus Analysis & Synthesis complaints that I have no architecture defined for entity B (unless I actualy provide Verilog code) but I don't want to define it, I want to have blackbox there instead. I have tried approach that I would define entity & empty architecture instead of component, but then all signals to this entity are optimized out and I don't really know how to replace it then with actual Verilog component when it is already defined as empty architecture... Is there any way to export post-synthesis netlist with blackbox inside? Also I need to do it automatically with TCL script, not in GUI. Now I do this, but it does not go through the first command
execute_flow -analysis_and_elaboration
create_partition -partition A -contents A
export_partition -partition A -post_fit off -post_synth on -routing off -qxp A.qxp
Thank you