Experienced Xilinx tool user needing Altera tool help

Hi,

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- Is there a qsf file (assuming that's the right file for these settings) with all of the Aria 10 dev kit I/O clearly identified, so I can use it as a template for future projects? If so, where might I find this?

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In package which comes with the Dev kit there should be reference design called "Golden Top Design". There you can find all pin assigments.

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- Is there another tool besides the pin planner that I should be using for such simple I/O config?

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The easiest way to make pin location and standart assigments is to use pin planner. After running Analysis and Synthesis in Pin planner you should see Node names from your top design file. Enter location assigments in "Location" column and standart assigments in "I/O standart" column. Also you can import them from another project (Assigments-> Import Assigments) or create your own .tcl script with pin assigments ect.