Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here.

1) I have a process where a signal is assigned a value using a big case statement based on a generic integer (it's basically a hard-coded lookup table). So there's really no sensitivity list (as the 'sensitive' variable is the generic integer), but also nothing to "wait" on. How do I code this? (right now I created a one-entry sensitivity list using my global reset - but that's a hack).

2) Quartus has a problem with me using a signal as a primary output. It wants me to use one signal in my code, and then 'assign' it to an output. It complains about the object not being a buffer? I found some -old- posts on this - but what's the right way to do this in 2012?

Thanks!

/j