Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Experienced Verilog coder has 2 Quartus-related VHDL questions..

Hi - after years of Verilog I'm coming up on VHDL. It's interesting. Two things I can't figure out, and since in both cases it's Quartus (not Modelsim) that's objecting, I thought i would ask here....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

--- Quote Start ---

the function approach worked out nicely as I had noted.

--- Quote End ---

Great!

But as I commented, beware calling complex functions inside a process, since the function calls will get executed every time the process runs. If the function is just being used to initialize a std_logic_vector, then perform that initialization outside the process.

Its a subtle issue, but it makes simulation significantly faster. Synthesis is identical for both methods.

Cheers,

Dave