Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Expected ALTPLL behaviour

Hello all, I would welcome some clarification on the expected behaviour of an ALTPLL when operating with a single compensated output clock in NORMAL mode. From the Stratix II GX Device Handboo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I would STRONGLY recommend using TimeQuest. That's what the report_timing command is used for. There's a learning curve, but once you ramp up you're going to like it 100x better. I don't know where you're at, and if you love the Classic Timing Analyzer and have been working for months to make constraints for it, then it might not be worth it, but if you're not too far along, and possibly if you are, I would recommend making the leap.

Is feedback_clk_in the name of the clock port, or are you using an external feedback for the PLL? I don't think so, but wanted to check based on the name. Anyway, your clock delay appears to be 2.821ns and your PLL is doing a -3.082ns shift, so it seems to be pretty close. Again, it won't be 0ns difference, but it's not in the ns range either.