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Altera_Forum
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17 years ago

Expected ALTPLL behaviour

Hello all, I would welcome some clarification on the expected behaviour of an ALTPLL when operating with a single compensated output clock in NORMAL mode. From the Stratix II GX Device Handboo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Do a report_timing -detail full_path where this clock domain is the source and destination clock. Have it output to a .txt file and then .zip it up and attach. It really doesn't make sense and just wanted to take a look. I usually do the Chip Editor approach to see if the PLL is next to the dedicated pin, which you've done, so not sure what's going on. (Chip Editor visualization is a lot easier than digging through the handbook tables...)