exec elab_debug error

Hi Pavee,

I understand it is very detail and time consuming, appreciate your help, I attached the whole project here just in case. It was originally a TI demo project. I am working on port it to Intel A10 GX dev Kit. so it is different chip on a different board and upgrade from Quartus 16 to 21.3.

I hope I can create a system level simulation environment and seems Quartus has this feature. I used to create a Modelsim project, add all related .v files. but the latest design methodology make this approach very hard, because the Platform Designer generate so many related files and they are scattered in some many different directory.

So the function call "Generate Simulator setup script for IP" is very critical and attractive. for all IP level modules it works fine. for example, the Intel emif example project will generate a top level testbench called ed_sim.ed_sim.

I think I need create this testbench by myself(Quartus has a Start Test Bench Template Writer). but I don't know how to include it to the .tcl. I need help/instruction/tutorial to add my system level testbench in the .tcl file.

for the project attached. there is a conflict while compiling. if enable "generate IP simulation model when generating IP", then the "analysys &Synthesis" has error.

if you disable the "generate IP simulation model when generating IP", then when you run "Generate Simulator setup script for IP", there will be a lot of error, So I have to keep toggling this generate IP simulation feature between simulation and synthesis. but this is not a critical issue.

Thank you for help.

David