Honored Contributor
Honored ContributorI can't comment on the specific errors, but here's what I would do:
1) Start by creating a new project, select the correct FPGA, and then add the Verilog files. Set the top-level file (files tab, select the file, right-click and set as top-level entity). See if things compile. Do not download that design to the board. 2) Setup the pin constraints. Use the .qsf file from the original project, or generate a Tcl file for the project that does not compile correctly, then copy the pin constraints from within that file. Build the design again. Check the pin assignments against a schematic. 3) Setup TimeQuest timing constraints. Setup the clock(s) and the I/O constraints. Build the design again. 4) Review the warnings in the Quartus synthesis window. Cheers, Dave
