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Altera_Forum
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14 years ago

error:Port "enable" does not exist in primitive "latch" of instance "u0"

When i was simulating my VHDL coding in Quartus II web edition i am getting the following errors: Error:Port "enable" does not exist in primitive "latch" of instance "u0" Error:can't elaborate u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Show the code.

What do you mean with "simulating my VHDL coding in Quartus II web edition" different from using modelsim-altera?