Error(16904) an enum variable may only be assigned to same enum typed variable or one of its values

Hi @OlegTerentiev

Sorry for the late reply. After checking, the error is due to quartus_syn switch from MCFU (Multiple File Compilation Unit) to SFCU (Single File Compilation Unit) for SystemVerilog files in Quartus Pro. This causes the enum to be defined twice in two separate compilation units (files) when the .svh header is included in the two separate files.

There is two workaround that you can use.

1. The easier one is to insert line below in the project .qsf file.

set_global_assignment -name VERILOG_CU_MODE MFCU

2. You can fix this problem by declaring and importing packages. You can include the svh file once in one of your files and simply import the package in all the other files where you need the enum definition. Attached the modified test case that you provided previously.

Attached information on Intel Quartus Prime Pro Edition follows the SFCU method:

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-getting-started.pdf

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.