Contributor
Super ContributorHi,
Do you have any further concern or consideration?
Does the problem being resolved?
Thanks,
Regards,
Sheng
ContributorHello @ShengN_Intel ,
I'm checking the .qar file.
When I open it, it doesn't includes the .vhdl file.
and the block only have an Avalon Memory Mapped Agent input port whereas the dummy module has the avalon_sink : in std_logic_vector(31 downto 0) and avalon_source : out std_logic_vector(31 downto 0) inputs. Why are not needed the Avalon Streaming Sink and Source ports?
When I run the compilation, "Timing requirements not met" error is given.
Super ContributorHi @RubenPadial ,
When I open it, it doesn't includes the .vhdl file.
In platform designer system .qsys, right-click dummy_0 -> Edit -> Files, i had put the dummy.vhd file for analyzing check screenshot.
Why are not needed the Avalon Streaming Sink and Source ports?
I had modified the design (attach below) to use both Avalon Streaming Sink and Avalon Streaming Source check screenshot.
When I run the compilation, "Timing requirements not met" error is given.
Because don't have the .sdc file. This is just a simple design example to show that there's no problem on the dummy.vhd. As mentioned before, make sure to re-generate the platform system to sync with the core file's update.
Thanks,
Regards,
Sheng
