Error(10500) simple_in_n_out program, straight from the book

Hi can anyone help me I'm an electronic engineering student trying to get practice, copid this from the book and its throws out Error (10500): VHDL syntax error at my_first_fpga.vhd(18) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"

the program

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity simple_in_n_out is

port (

--Inputs

in_1 : in std_logic;

in_2 : in std_logic;

in_3 : in std_logic;

--Outputs

out_1 : out std_logic;

out_2 : out std_logic;

);

end entity simple_in_n_out;

architecture simple_in_n_out_arch of simple_in_n_out is

begin

---------Design Implementation---------

out_1<= in_1 AND in_2 AND in_3;

out_2<= in_1 OR in_2 OR in_3;

end architecture simple_in_n_out_arch;