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Altera_Forum's avatar
Altera_Forum
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19 years ago

Error: WYSIWYG I/O

I get the following error when I run Quartus on my design. I know I have seen it before but cannot remember how to fix it. Your help will be greatly appreciated.

Error: WYSIWYG I/O primitive "qdrii:u_qdr|qdr:auk_qdrii_mw_wrapper|qdr_auk_qdrii_sram:qdr_auk_qdrii_sram_inst|qdr_auk_qdrii_sram_datapath:auk_qdrii_sram_datapath|qdr_auk_qdrii_sram_capture_group_wrapper:auk_qdrii_sram_capture_group_wrapper|qdr_auk_qdrii_sram_cq_cqn_group:auk_qdrii_sram_cq_cqn_group|cqn_inst" is not properly connected to a top level pin

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Are you using a third-party synthesis tool? If so, this is probably one of the cases where you have to tell the tool not to put an I/O cell ATOM between the port of the black box where you instantiated the memory interface IP and the top-level port corresponding to the device pin. If the IP has the I/O cell ATOM ("WYSIWYG I/O primitive" in your message), then the third-party tool needs to connect it up the hierarchy to the device pin with a simple wire connection in the .edf or .vqm file.

    If you are using Quartus integrated synthesis, maybe you have some logic between the I/O cell ATOM in the IP and the device pin. Or maybe you just failed to make the connection in the RTL.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    If you are using Synplify pro,

    tell quartus in the EDA tool preference that the entry tool is synplify pro.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    @ shempington

    could you find a solution for that?

    I am also getting the same error.