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Altera_Forum's avatar
Altera_Forum
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18 years ago

Error with SOPC generated files

I am using SDRAM controller in SOPC builder, when compiling the project with QuartusII following error appears.

Any help on how to resolve this.

Error: IO_PIN atom "ddr_dqs_to_and_from_the_ddr_sdram_0[0]" has port DQSUPDATEEN that must be connected to the dqsupdate output of a DLL because the dqs_ctrl_latches_enable parameter is set to true

Error: IO_PIN atom "ddr_dqs_to_and_from_the_ddr_sdram_0[1]" has port DQSUPDATEEN that must be connected to the dqsupdate output of a DLL because the dqs_ctrl_latches_enable parameter is set to true

Thanks a lot,

Sasi

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I think you get this error because first you have to assign that pins (ddr_dqs_sdram[0] and [1]) as "Use as regular I/O" in Assignements\Settings\Device\Device and Pin Options\Dual Purpose Pins

    try it
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I set all the IO's to "Use as regular I/O" option. It did not solve the problem.

    Infact the signals are "ddr_dqs_to_and_from_the_ddr_sdram_0[0]" not there in the top module.

    Please let me know if you want me to try anything else.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    There are two possibilities for this error:

    1 - You don't have something connected correctly. Verify that all your DQS pins to/from the DDR2 core are properly connected to top level DQS pins.

    2 - Part of your design is being synthesized away because it is not being used. If you've instantiated the DDR2 RAM but you're not actually using it, the logic will be synthesized away and you will get the error shown.

    Jake