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Altera_Forum's avatar
Altera_Forum
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14 years ago

Error with operators

Everytime i try to use an operator (+, -,...), I have the following error:

Error(10327) - can't determine definition of operator "-", found 0 possible definitions.

Here is the full code, but the problem is at the bold part.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

ENTITY reg_b IS

PORT ( clk, dec: IN STD_LOGIC;

D: IN STD_LOGIC_VECTOR(3 downto 0);

B: OUT STD_LOGIC);

END reg_b;

ARCHITECTURE comportamento OF reg_b IS

signal Q: std_logic_vector(3 downto 0);

signal Q_integ: integer range 0 to 15;

BEGIN

PROCESS (clk)

BEGIN

IF clk'EVENT AND clk = '1' THEN

Q<=D;

END IF;

END PROCESS;

Q_integ <= to_integer(unsigned(Q));

Process(dec)

Begin

If dec'event AND dec='1' Then

q_integ <= q_integ - '1';

IF Q='0' Then B<='1';

End IF;

END IF;

End Process;

END comportamento;

I appreciate some help.

Thank you.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Several problems here.

    For a start, you cannot assing Q_integ from a process and outside the process. You can only assign it in one place.

    secondly try

    Q_integ <= Q_integ - 1; --instead of '1'

    But in simulation you're going to get an error when it tries to go below 0.

    So, change the definition of Q_integ to

    signal Q_integ : unsigned(3 downto 0);

    But you're going to see 'XXXX' when you try and simulate it unless you do what I said for the first problem.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    OK, the subtract operator works now, thank you.

    But if I can't assign a value to a variable in both places, or in two process, how can I make a VHDL software that do: When I activate one input, I take an input vector value and save in a variable, and each time I activate input B, i decrement that variable by 1.

    Here is what I did, but i have an error saying Q_int depends on multiple clocks.

    i/o:

    clk, dec: IN STD_LOGIC;

    D: IN STD_LOGIC_VECTOR(3 downto 0);

    signals:

    signal Q: std_logic_vector(3 downto 0);

    signal Q_int: integer range 0 to 15;

    PROCESS (clk, dec)

    BEGIN

    IF clk'EVENT AND clk = '1' THEN

    Q<=D;

    Q_int <= to_integer(unsigned(Q));

    END IF;

    If dec'event AND dec='1' Then

    Q_int<=Q_int-1;

    END IF;

    END PROCESS;

    Thank You!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You need to be careful what you say.

    A signal (like Q_int) is not a variable. It is not updated until a process suspends.

    A variable in VHDL is updated immediatly, like a C variable.

    VHDL is not a programming language. its a description language. This is a very important difference.