Error with operators

OK, the subtract operator works now, thank you.

But if I can't assign a value to a variable in both places, or in two process, how can I make a VHDL software that do: When I activate one input, I take an input vector value and save in a variable, and each time I activate input B, i decrement that variable by 1.

Here is what I did, but i have an error saying Q_int depends on multiple clocks.

i/o:

clk, dec: IN STD_LOGIC;

D: IN STD_LOGIC_VECTOR(3 downto 0);

signals:

signal Q: std_logic_vector(3 downto 0);

signal Q_int: integer range 0 to 15;

PROCESS (clk, dec)

BEGIN

IF clk'EVENT AND clk = '1' THEN

Q<=D;

Q_int <= to_integer(unsigned(Q));

END IF;

If dec'event AND dec='1' Then

Q_int<=Q_int-1;

END IF;

END PROCESS;

Thank You!