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Altera_Forum's avatar
Altera_Forum
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17 years ago

Error while simulating with ModelSim

Hello guys

I'm still a very beginner in Quartus II and FPGA programming in general.

I'm still trying to run the simple example of hello world available in the quartus folder using the altera manual here www.altera.com/literature/an/an351.pdf (http://www.altera.com/literature/an/an351.pdf) and after making all the steps (making the design with SOPC builder, adding the file in the Quartus II) i'm trying to simulate with ModelSim (having the "hello world" signal after it has been converted from C language to VHDL).

I have the following errors

--- Quote Start ---

# ** Error: (vcom-11) Could not find ./vhdl_libs/altera.altera_europa_support_lib.# ** Error: C:/SAMY/SOPC_Test/onchip_memory2_0.vhd(19): (vcom-1195) Cannot find expanded name: 'altera.altera_europa_support_lib'.# ** Error: C:/SAMY/SOPC_Test/onchip_memory2_0.vhd(19): Unknown record element "altera_europa_support_lib".

--- Quote End ---

Then

--- Quote Start ---

# ** Error: C:/SAMY/SOPC_Test/onchip_memory2_0.vhd(32): VHDL Compiler exiting# ** Error: C:/Applications/Modeltech/win32/vcom failed.

--- Quote End ---

But as i searched in several posts, i things the last two errors are very commun and may just mean that the simulation was aborted.

Any Ideas?!

It's kinda urgent. Big thanks for your help !

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You need to compile the altera_europa_support_lib.vhd file found in the

    altera\quartus\libraries\vhdl\altera

    sub-directory.

    Hope this helps
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Yes in fact, I found the lib files that were missing.

    After i finish the IPs architecture with the SOPC builder, i succeded in generating and also in building the project with the Nios IDE but the weird fact is that the vhd files (that were generated) are not added to the quartus project and so i cannot simulate the results with ModelSim.

    Any ideas?!

    Thanks alot
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    In SOPC Builder on the System Generation page there is a button "Run Simulator". When you click this Modelsim should open with the correct project and run a script which creates some shortcuts - a description of these should appear in the transcript window. You should then be able to compile the VHDL and memory contents each with one command.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank you for your response. Thanks to your help i made big progress and i'll soon be able to help those who have the same problem i had (specially while trying to simulate the very simple "hello world" example, Altera AN 351).

    In fact now i'm able to add the IPs (with SOPC Builder), to generate the VHDL files, create and build the project with Nios IDE, and then running the simulation with modelsim by entering "s". Though i can't find the "hello world" phrase in the txd signal ( signal out of the UART according to documentation).

    The error seem to be in the UART since the uart rxd signal is Undefined (in red in modelsim) and txd value has always "1" so i suspect the program is not processed (simulated actually) or there's a communication problem (nios - uart) or even the architecture i've designed with SOPC is malfunctionning. I've used 3 IPs : the cpu nios, the onchi memory and the UART.

    Please any ideas? (this shoul be the final step ! )

    thanks and read you soon
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Just one thought - how long are you running your simulation for? You may have to run it for a while to see something come out depending on your baud rate and what the NIOS code is doing.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank you, that was the problem. I was running the simulation for 200 us thinking the "hello world" shoul appear in the txd_data from the very beginning, i had the right signal after about 500us, very stupid !!

    Now i can help any who wants to simulate the example of the AN 351 altera example (hello world).

    For me, the next step is to simulate the hole architecture without the Nios IDE, using simulink and the files generated by the sopc builder (and so quartus)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    by the way, anyone knows where i can find examples (other than those provided with the quartus,...) of architectures designed with the SOPC builder and simulated with modelsim (without using the Nios IDE) ??

    thx
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    The error seem to be in the UART since the uart rxd signal is Undefined (in red in modelsim) and txd value has always "1" so i suspect the program is not processed (simulated actually) or there's a communication problem (nios - uart) or even the architecture i've designed with SOPC is malfunctionning. I've used 3 IPs : the cpu nios, the onchi memory and the UART.

    --- Quote End ---

    I have the same problem. I was running the simulation for 800us and got an error:

    # 2281 ns: ERROR: cpu_test_bench/M_en is 'x'

    # Break in Module cpu_test_bench at ../cpu_test_bench.v line 572

    I use Quartus 9.1 and NiosII EDS 9.1. I don't connect a hardware board to my computer.

    Any ideas?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    With 9.1 SP2 I get

    # Error: ?????????

    #

    # Unable to replace existing ini file (modelsim.ini). File can not be renamed.

    Does anyone else?