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The error seem to be in the UART since the uart rxd signal is Undefined (in red in modelsim) and txd value has always "1" so i suspect the program is not processed (simulated actually) or there's a communication problem (nios - uart) or even the architecture i've designed with SOPC is malfunctionning. I've used 3 IPs : the cpu nios, the onchi memory and the UART.
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I have the same problem. I was running the simulation for 800us and got an error:
# 2281 ns: ERROR: cpu_test_bench/M_en is 'x'
# Break in Module cpu_test_bench at ../cpu_test_bench.v line 572
I use Quartus 9.1 and NiosII EDS 9.1. I don't connect a hardware board to my computer.
Any ideas?
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