Error while running simulation

From what you describe it looks as if in this instance modelsim does not like the 'high attribute being applied to anything but a type or subtype. Maybe this is related to the fact that it is applied to a port whose length is specified by a generic

Without looking at the LRM I do not know whether this is an issue with modelsim or Quartus

A work around would be to change the code as follows:

subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);

type memory_t is array((2**ADDR_WIDTH) - 1 downto 0) of word_t;

-- Declare the RAM signal.

signal ram : memory_t;

-- Register to hold the address

signal addr_reg : natural range 0 to (2**ADDR_WIDTH) - 1;

i.e. use the generic to control the "high" value of address

Hope this helps