Error while running simulation

I was just checking out the design template for "Single port RAM" which was provided in Quartus II 8.0. The model compiles in Quartus II but gives me an error in ModelSim AE 6.1g.

here is the template:

"

-- Quartus II VHDL Template

-- Single port RAM with single read/write address

library ieee;

use ieee.std_logic_1164.all;

entity ram_2 is

generic

(

DATA_WIDTH : natural := 8;

ADDR_WIDTH : natural := 3

);

port

(

clk : in std_logic;

addr : in natural range 0 to (2**ADDR_WIDTH) - 1;

data : in std_logic_vector((DATA_WIDTH-1) downto 0);

we : in std_logic := '1';

q : out std_logic_vector((DATA_WIDTH -1) downto 0)

);

end entity;

architecture rtl of ram_2 is

-- Build a 2-D array type for the RAM

subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);

type memory_t is array(addr'high downto 0) of word_t;

-- Declare the RAM signal.

signal ram : memory_t;

-- Register to hold the address

signal addr_reg : natural range 0 to addr'high;

begin

process(clk)

begin

if(rising_edge(clk)) then

if(we = '1') then

ram(addr) <= data;

end if;

-- Register the address for reading

addr_reg <= addr;

end if;

end process;

q <= ram(addr_reg);

end rtl;

"

and here is the error :

"# ** Error: C:/altera/80/quartus/Test/RAM_Tst_1/ram_2.vhd(30): Prefix (signal "addr") for attribute "high" is not a type mark.# ** Error: C:/altera/80/quartus/Test/RAM_Tst_1/ram_2.vhd(36): Prefix (signal "addr") for attribute "high" is not a type mark.# ** Error: C:/altera/80/quartus/Test/RAM_Tst_1/ram_2.vhd(54): VHDL Compiler exiting# ** Error: C:/altera/80/modelsim_ae/win32aloem/vcom failed.

"

Please Advice...